The invention relates to defect analysis in semiconductor device assemblies, and more particularly to techniques for accurately analyzing defects within semiconductor devices using laser scanning microscopes.
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
To increase the number of pad sites available for a die, to reduce the electrical path to the pad sites, and to address other problems, various chip packaging techniques have been developed. One of these techniques is referred to as controlled collapse chip connection or xe2x80x9cflip-chipxe2x80x9d packaging. With packaging technology, bonding pads of the die include metal (solder) bumps. Electrical connection to the package is made when the die is xe2x80x9cflippedxe2x80x9d over and soldered to the package. Each bump connects to a corresponding package inner lead. The resulting packages are low profile and have low electrical resistance and a short electrical path. The output terminals of the package, which are sometimes ball-shaped conductive bump contacts, are typically disposed in a rectangular array. These packages are occasionally referred to as xe2x80x9cBall Grid Arrayxe2x80x9d (BGA) packages. Alternatively, the output terminals of the package may be pins and such packages are commonly known as pin grid array (PGA) packages.
Once the die is attached to such a package the back side portion of the die remains exposed. The transistors and other circuitry are generally formed in a very thin epitaxially-grown silicon layer on a single crystal silicon wafer from which the die is singulated. The side of the die including the epitaxial layer containing the transistors and other circuitry is often referred to as the circuit side or front side of the die. The circuit side of the die is positioned very near the package and opposes the back side of the die. Between the back side and the circuit side of the die is bulk silicon.
The positioning of the circuit side near the package provides many of the advantages of the flip chip. However, in some instances orienting the die with the circuit side face down on a substrate is disadvantageous. Due to this orientation of the die, the transistors and circuitry near the circuit side are not directly accessible for testing, modification or other purposes. Therefore, access to the transistors and circuitry near the circuit side is from the back side of the chip.
With flip-chip and other packaging technologies, techniques have been developed to analyze the circuit even though the integrated circuit (IC) is buried under the bulk silicon. For example, near-infrared (nIR) microscopy is capable of imaging the circuit because silicon is relatively transparent in these wavelengths of the radiation. However, because of the absorption losses of nIR radiation in silicon, it is generally required to thin the die to less than 100 microns in order to view the circuit using nIR microscopy. For a die that is 725 microns thick, at least 625 microns of silicon is removed before nIR microscopy can be used. Another example method used for analysis of semiconductor devices via the back side is laser scanning microscopy (LSM). LSM involves scanning an incident beam across a surface of a specimen and detecting the intensity of an exit beam emerging from the surface. Using the exit beam, structures within the specimen can be imaged.
In addition to imaging a semiconductor device, other methods for analyzing semiconductor devices include detecting a response via the back side. For example, circuitry within the semiconductor device can be excited to generate a detectable response. Various methods are available for exciting circuitry and include using a power supply, stimulating circuitry with an electromagnetic radiation source, and directing an ion beam at the back side. Using these techniques, a characteristic of the semiconductor device can be determined.
The aforementioned example techniques are useful for analyzing semiconductor devices. However, problems have been observed in imaging and analyzing the circuit and stimulating device components in accordance with the above described techniques. With imaging methods, significant background laser intensity levels have been observed. While stimulating the electronic components, weak response levels have been experienced, and control of the stimulation is hindered via the existence of reflections or interference, in the device. In addition, interference patterns from reflections and other sources impede the efficacy of imaging processes. These and other problems associated with reflections in semiconductor device manufacture and analysis have been a hindrance to the advancement of semiconductor technologies.
The present invention is exemplified in a number of implementations and applications, some of which are summarized below. According to an example embodiment of the present invention, an electronic circuit is formed upon a front side surface of a semiconductor device having a back side opposite the front side. At least one layer of antireflective material is formed within substrate in the back side of the semiconductor device. The circuit is stimulated and the response to the stimulation is analyzed. The use of the antireflective layer reduces reflections including interference patterns, and improves the analysis of the device.
According to another example embodiment of the present invention, a semiconductor device is manufactured. The device comprises a front side and a back side opposite the front side. An electronic circuit is formed upon the front side surface, and at least one layer of antireflective material is formed in the substrate of the back side. The antireflective material is configured and arranged to prevent interference patterns from emanating from or reflecting back to the device.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description which follow more particularly exemplify these embodiments.